At the SAFE Forum (Samsung Advanced Foundry Ecosystem), Samsung revealed its plans for future semiconductor nodes. Last year, the company unveiled the Exynos 2600, the first 2nm smartphone chip – this one was made on the SF2 node as Samsung calls it.
Next up is SF2P, which will reduce power consumption by 26% and raise clock speeds by 15%. The new node is only partially responsible for these improvements. Shin Jong-shin, VP of the Design Platform Development Team at Samsung Foundry, attributes more than half of the gains to DTCO.
DTCO, or Design-Technology Co-Optimization, is a chip-making approach that combines semiconductor manufacturing methodology and chip design – traditionally, these are two separate steps in building a new chip, but working on them simultaneously enables better optimized designs. This leads to higher speeds, lower power and even cost savings.
SF2P+ will come next – mass production is expected to start between 2027 and 2028. There is another node in the works too, SF2X, but that one will be optimized for AI hardware.
Samsung is also working on ways to pack more SRAM onto chips. SRAM is used to build the registers and the cache of a CPU or GPU. It’s super fast, but takes up more room than DRAM – to put things into perspective, a typical SRAM cell (which stores a single bit, i.e. a 0 or a 1) needs 6 transistors, while a DRAM cell needs only 1 transistor.
The Nvidia Rubin GPU (fabbed on TSMC’s N3 node) has 128MB of on-die SRAM. Samsung and Groq are working on an LLM accelerator that will have more than 500MB of SRAM and this is on the older 4nm node. Samsung-backed Rebellions showed off the REBEL-100 AI accelerator, which is currently being produced on Samsung’s 4nm node.
After the 2nm era, Samsung will transition to 1.4nm nodes starting with SF1.4, which is scheduled for 2029 mass production. This will be followed by SF1.4+ in 2030. SF1.4 was originally scheduled for 2027, but the timeline was pushed back a couple of years ago.
